Biography: Yoshinobu Higami received his B.E., M.E., and D.E. degrees from Osaka University in 1991, 1993 and 1996, respectively. Currently he is a professor at Graduate School of Science and Engineering, Ehime University. In 1998 and 2006, he was also an honorary fellow at University of Wisconsin-Madison, U.S.A. He received the IEICE Best Paper Award in 2005 and 2012. His research interests include test generation, design for testability and fault diagnosis of logic circuits. He is a senior member of the IEEE and a member of IEICE and IPSJ.
Speech Title: Test Generation Methods for Delay Faults on Clock Lines
Abstract: Consideration of delay faults during testing of modern high speed LSIs is important and essential. Many of the conventional methods focused on detection of faults at gate lines in the combinational part, but few of them focused on faults on clock lines. In this research, we propose a test generation method for delay faults on clock lines assuming launch-on-capture test environment. The proposed method employs a standard stuck-at ATPG tool to generate target test vectors. Moreover, we consider gate transition faults in the presence of clock delay faults, and propose a test generation method for detecting these faults. The effectiveness of the proposed methods has been confirmed by experiments for benchmark circuits.